Generally, a process for preparing a semiconductor chip comprises a process for forming fine patterns on a wafer and a process for packaging the wafer after polishing it, so as to meet standards of the final device.
Here, the process for packaging comprises a step of wafer inspecting, wherein a semiconductor chip is inspected for defectives; a step of dicing, wherein a wafer is cut to separate into each chip; a step of die bonding, wherein the separated chip is attached to a circuit film or a loading plate of a lead frame; a step of wire bonding, wherein circuit patterns of the circuit film or the lead frame are connected to chip pads provided on the semiconductor chip, with an electrical connecting means such as a wire; a step of molding, wherein the outside of the semiconductor chip is surrounded with a sealant to protect interior circuits of it and the other parts; a step of trimming, wherein a dambar connecting a lead to a lead is cut; a step of forming, wherein the lead is bent into the desired shape; and a step of finished product inspecting, wherein the finished package is inspected for defectives.
Furthermore, in said step of dicing, the wafer is cut in a certain thickness with a diamond wheel, and the like. Here, to fix the wafer, an adhesive film for dicing die bonding is laminated on the back side of the wafer, on which patterns are not formed, under an appropriate temperature condition. However, in case of performing the step of dicing under said condition, an excessive pressure or a mechanical impact is applied thereto to cause chippings due to the wafer damage, and burrs which are able to cause contamination of patterns. At a recent while the thickness of wafer become thinned due to a small size of the packaging and the dicing conditions become severe for increase of production efficiency, said problems frequently happen. Especially, while the thickness of wafer become thinned, there are many cases in which even burrs having a level without any problem formerly, climb onto a die, and they cause defectives of the semiconductor chip by contaminating the patterns.
Most conventional techniques for decreasing such burr incidence were almost methods for regulating physical properties of dicing films and die bonding films. However, in case of changing physical properties of said films to reduce the incidence of burrs, there is relatively a limit to physical properties such as reliability in die bonding process or dicing process.
Japanese Unexamined Patent Publication No. 2007-19478 discloses a method for carrying out dicing as a technique which prevents to scatter wafer fragments without practicing back grinding in the dicing, in which a dicing depth is controlled in each part of wafer and height of a dicing blade is slowly changed (ascended) in specific parts.
However, in the method disclosed in said prior document, dicing is carried out to the base film of the dicing film as the conventional dicing methods. In this case, the expanding and pick-up step are carried out in a condition that the die bonding film, being major component of burrs, is completely cut. Here, there is a problem to cause contamination of die, since burrs of the die bonding film having relatively weak adhesion strength are scattered over die.